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[VHDL-FPGA-Verilog] CAST_sdr_sdram_ctrl-xact

Description: Single Data Rate Mobile SDRAM Controller Core with AHB Interface
Platform: | Size: 733184 | Author: gosha | Hits:

[Other] sdram_control

Description: sdram 控制器的源代码及说明文档，综合，仿真。是一个很好的sdram控制器学习资料-provide sdram controller source code and documentation, integration, simulation. Is a very good learning materials about sdram controller
Platform: | Size: 3642368 | Author: 冯谋朝 | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
Platform: | Size: 678912 | Author: liujie | Hits:

[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl

Description: DDR SDRAM控制器的VHDL代码已经测试-DDR SDRAM controller VHDL code
Platform: | Size: 13312 | Author: tom | Hits:

[Other] FPGAbasedSDRAMControll

Description: 基于FPGA的SDRAM控制器 Realization FPGA-based SDRAM Controller with Verilog-FPGA-based SDRAM Controller Realization FPGA-based SDRAM Controller with Verilog
Platform: | Size: 1755136 | Author: monica-sun | Hits:

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
Platform: | Size: 488448 | Author: peace | Hits:

[VHDL-FPGA-Verilog] c_xapp858

Description: 这是xilinx应用指南xapp858的中文版本。本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex™ -5 I/O 都具有的输入串行器/ 解串器 (ISERDES) 和输出双倍数据速率 (ODDR) 的功能。-This is the xilinx application note xapp858 the Chinese version. This application note describes the interface used to achieve high-performance DDR2 SDRAM controller and data acquisition technology. This data collection technique used in each Virtex ™ -5 I/O has an input serializer/deserializer (ISERDES) and output double data rate (ODDR) function.
Platform: | Size: 447488 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] burstpage

Description: SDRAM控制器在FPGA实现源代码，能实现burst传输-SDRAM controller in FPGA realization of the source code, can achieve burst transfer
Platform: | Size: 253952 | Author: 弘历 | Hits:

[Other] NewFolder

Description: sdram controller code
Platform: | Size: 3072 | Author: prashanthi | Hits:

[Embeded Linux] DS-0050_OXE800SE_datasheet

Description: SATA NAS SOC，200MHz ARM926EJS核 SATA接口的NAS用处理器，集成USB2.0 HOST接口，Ethernet控制器，DDR SDRAM控制器，PCI HOST接口，可以扩展PCI外设。-SATA NAS SOC，NAS COntroller with 200MHz ARM926EJS core, intergated SATA controller，USB2.0 HOST controller，Ethernet MAC controller，DDR SDRAM controller，PCI HOST。-The OXE800SE is a highly integrated, powerful network attached storage controller for bridging between Ethernet and SATA hard disks.
Platform: | Size: 317440 | Author: lzch | Hits:

[VHDL-FPGA-Verilog] verilog_sdram

Description: SDRAM读写控制的实现与Modelsim仿真,采用verilog HDL编写-sdram controller and simulate with modelsim
Platform: | Size: 2176000 | Author: bigchop ma | Hits:

[Other] SDRAM_VHDL

Description: VHDL SDRAM Controller
Platform: | Size: 44032 | Author: terra02 | Hits:

[VHDL-FPGA-Verilog] sdram_pci

Description: 基于SDRAM的PCI采集程序，PCI9054控制器+SDRAM控制器Verilog源代码，，已经SignalTap调试通过。-SDRAM PCI-based acquisition program, PCI9054 Controller+ SDRAM controller Verilog source code, has SignalTap through debugging.
Platform: | Size: 3166208 | Author: wangbo | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_2Port

Description: 双端口SDRAM控制器，将SDRAM虚拟成两个端口，已经在ALTER DE2开发板的硬件上验证通过，采用Verilog HDL语言编写。-Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language.
Platform: | Size: 11264 | Author: | Hits:

[VHDL-FPGA-Verilog] sdram_controller

Description: SDRAM 控制器的 verilog 源代码, 针对Micron 的SDRAMS设计,支持全部的指令, 已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SDRAM controller verilog source code, for Micron' s SDRAMS designed to support all of the instructions, the logic has been verified, and actually used in chip design, as a module to work.
Platform: | Size: 9216 | Author: Jerd Hu | Hits:

[Software Engineering] DDR2deFPGAsheji

Description: 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
Platform: | Size: 2525184 | Author: 张桃源 | Hits:

[VHDL-FPGA-Verilog] altera_avalon_sdram_slave

Description: Altera avalon sdram controller salve.
Platform: | Size: 5120 | Author: liubo | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl.tar

Description: sdram controller VHDL source code
Platform: | Size: 90112 | Author: datonglii | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl

Description: sdram 控制器 含testbench-sdram controller with testbench
Platform: | Size: 29696 | Author: kewell | Hits:

[VHDL-FPGA-Verilog] SDRAMcontroler

Description: SDRAM控制器，Verilog代码以及相关文档-SDRAM controller, Verilog code, and related documentation
Platform: | Size: 1743872 | Author: 李涛 | Hits:
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